Profile
Name:
Jason
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20,081
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Style:
Educational
Age:
25
Joined:
Jul 24, 2009
Subscribers:
245
Website:
The official YouTube channel for reprogrammable XMOS embedded parallel processors.
XMOS programmable chips bring together the capabilities of processors, DSPs, ASICs and FPGAs
(This account is maintained by @jason_mayes)
Follow/tweet at us on Twitter:
http://www.twitter.com/xmos @XMOS
Join our HUGE community at:
http://www.xcore.com/
XMOS programmable chips bring together the capabilities of processors, DSPs, ASICs and FPGAs
(This account is maintained by @jason_mayes)
Follow/tweet at us on Twitter:
http://www.twitter.com/xmos @XMOS
Join our HUGE community at:
http://www.xcore.com/
About Me:
Country:
United Kingdom
Companies:
XMOS
Interests:
embedded processors, processors, robotics, DSP, Ethernet AVB, LED tile displays, parallel processors, XMOS, education, university, hardware, software, USB, motor control, audio systems, networking, XC, software defined silicon, low power, low cost, high performance
Books:
Programming XC on XMOS Devices, The XMOS XS1 Architecture
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I am posting this as I suspect it to be true.
Lack of a CPUID instruction. The Intex x86 family has this, and it is one of the few good ideas in x86.
Each time you revise your CPUs or GPUs you need to add it :
A separate 32 bit register would do fine, or use an existing lesser used one.
Use calling conventions like CPUID, with 0 ... 64 as inputs. Problem solved.