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ChipEnet
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ChipEnet uploaded and replied to a comment from Mk2SoLDiEr
Wow, it's been 3 years. Time has flew by quick. With the latest process advances, serial transceivers & even standard IO operating in LVDS or CML modes are ridiculously fast. FPGA IO bandwidth is not an issue. You can have as much as you want on the cheapest FPGAs. The bigger problem is the control of all this data, RTOS & cpus are just too slow. Cable bandwidth hasn't improved too much but HDMI cables are cheap now. Sorry for not finishing the exercise.
$49 FPGA board with 500 MBytes/sec IO bandwidth
$49 Avnet Spartan 3A FPGA evaluation board with added dual Ethernet Gb PHY daughter card.
500 MBytes/sec of IO bandwidth across 4 full duplex 125 Mhz channels. Two rx channels and
two tx channels... -
ChipEnet uploaded a video
Ethernet Switch 2Port Gb 100Mb
Top trace = 100Mb send TX DV, 2nd trace = Gb receive, RX DV
3rd trace = Gb send TX DV, bottom trace = 100Mb RX DV
The duration of the active high DV signals = packet size.
This video show... -
ChipEnet uploaded a video
Ethernet Switch test setup
SP601 board with 100Mb port + Gb port connected to SP605 board with 6 port FMC
adapter card. SP601 board send packets & receive packets from the SP605 board.
No software. -
ChipEnet uploaded a video
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ChipEnet uploaded a video
ChipEnet IEEE1588 clock
Video of ChipEnet IEEE 1588 slave clock locking to master clock under
1. steady state condition
2. sudden change in master clock frequency, increase in frequency by 1.5Mhz
3. random dela...